1. Field of the Invention
The invention generally relates to solid-state imaging devices, cameras, and electronic devices. More particularly the invention relates to a solid-state imaging device including in a pixel a convertor for converting electric charges generated by a photoelectric conversion element to pixel signals, such as CMOS image sensor, for example. The invention also relates to a camera and an electronic device each provided with the solid-state imaging device. The CMOS image sensor is referred herein to an image sensor fabricated at least partially utilizing the CMOS process.
2. Description of the Related Art
A CMOS image sensor is a solid-state imaging device provided by including a plurality of pixels arranged two-dimensionally, each pixel including a photoelectric conversion element and several pixel transistors or so-called MOS transistors, and by being configured to convert electric charges generated by the photoelectric conversion element to image signals to be readout subsequently. In recent years, the CMOS image sensor has been attracting much attention, as its application spread to various imaging devices such as cameras for use in mobile phone, digital still cameras, digital camcorders, and other similar devices.
FIG. 1 illustrates an example of a CMOS image sensor generally known. The CMOS image sensor 1 is provided, for example, by including an imaging section 4 which has a plurality of pixels 3 (unit cells) arranged in a two-dimensional array, each of the pixels including a photodiode serving as photoelectric conversion element 2 and several pixel transistors (MOS transistors), and by including peripheral circuits.
On receiving light with the photoelectric conversion element 2, signal charges generated by the photoelectric conversion are accumulated. These pixel transistors are provided in the present example as four-transistor circuit configuration including a transfer transistor 6, a reset transistor 7, an amplifying transistor 8, and a selection transistor 9. The transfer transistor 6 serves as the transistor for transferring signal charges accumulated in the photoelectric conversion element 2 to a floating diffusion (FD), i.e., the gate of the amplifying transistor 8. The reset transistor 7 is the transistor for resetting gate potential of the amplifying transistor 8. The amplifying transistor 8 is for amplifying the signal charges. The selection transistor 9 is for selecting an output pixel.
In a pixel 3, the source of the transfer transistor 6 is connected to the photoelectric conversion element 2, and the drain of the transfer transistor is connected to the source of the reset transistor 7. To the gate of the transfer transistor 6, a transfer signal wiring 11 is connected to control the gate potential of the transfer transistor. For the reset transistor 7, the drain thereof is connected to the source voltage supply line (hereinafter referred to as power supply wiring) 10 and the gate thereof is connected to a reset signal wiring 12 for controlling the gate potential. For the amplifying transistor 8, its drain is connected to the power supply wiring 10, its source is connected to the drain of the selection transistor 9, and its gate is connected to the floating diffusion (FD) between the transfer transistor 6 and the reset transistor 7. For the selection transistor 9, its source is connected to the pixel output line 14 and its gate is connected to the selection signal wiring 13 for controlling gate potential.
A transistor 16 for supplying a constant current is connected to the pixel output line 14 so as to supply a constant current to a selected amplifying transistor 8, operate the amplifying transistor 8 as the source follower, and make potential be generated onto the pixel output line 14 such that this potential has a certain fixed voltage difference relative to the gate potential of the transistor 8. To the gate of the transistor 16, a constant potential supply line 17 is connected for supplying fixed potential such that the transistor 16 operates in the saturation region for supplying a fixed current.
The numeral 32 represents ground potential for controlling the potential of semiconductor well region for suitably forming the pixel, while the numeral 33 represent a ground wiring.
On the other hand, a vertical selection unit 21, a column selection unit 22, and a CDS (correlated double sampling) circuit 23 are provided as the peripheral circuits. In addition, disposed for each row of the pixels 3 are a row selection AND circuit 25 having the output terminal thereof connected to the transfer signal wiring 11, another row selection AND circuit 26 having the output terminal thereof connected to the reset signal wiring 12, and still another row selection AND circuit 27 having the output terminal thereof connected to the selection signal wiring 13.
To one input terminal of the row selection AND circuit 25 in each row, a pulse terminal 28 is connected for supplying a transfer pulse to the transfer signal wiring 11, while an output from the vertical selection unit 21 is connected to the other input terminal of the AND circuit 25. To one input terminal of the row selection AND circuit 26 in each row, a pulse terminal 29 is connected for supplying a reset pulse to the reset signal wiring 12, while the output from the vertical selection unit 21 is connected to the other input terminal. To one input terminal of the row selection AND circuit 27 in each row, a pulse terminal 30 is connected for supplying a selection pulse to the selection signal wiring 13, while the output from the vertical selection unit 21 is connected to the other input terminal.
With such configuration, each control pulse is supplied only to the signal wirings connected to the row selected by the vertical selection unit 21. The readout operation from each pixel 3 is carried out as follows by applying drive signals shown in FIG. 2.
A transfer signal (pulse) S1 shown in FIG. 2 is supplied to the transfer signal wiring 11, a reset signal (pulse) S2 is supplied to the reset signal wiring 12, and a selection signal (pulse) S3 is supplied to the selection signal wiring 13.
First, by supplying a selection pulse S3 and a reset pulse S2, the selection transistor 9 and the reset transistor 7, which are connected to the row to be presently readout, are brought to the conduction state, and the potential of the gate (so-called floating diffusion FD) of the amplifying transistor 8 is reset. After turning the reset transistor 7 to be non-conductive, the voltage corresponding to the reset level of each pixel 3 is readout to the CDS circuit 23 at the subsequent stage. Next, by supplying a transfer pulse S1, the transfer transistor 6 is turned to be conductive, and the charges accumulated in the photoelectrical conversion element 2 are transferred to the floating diffusion, i.e., the gate of the amplifying transistor 8. Subsequent to the charge transfer, the transfer transistor 6 is brought to the non-conduction state and the voltage at the signal level corresponding to the amount of accumulated charges is readout to the CDS circuit 23 at the subsequent stage.
With the CDS circuit 23, the difference between the reset level readout previously and the signal level is computed, whereby fixed pattern noise is offset, which may be generated in the amplifying transistor by the variation of threshold voltage Vth and similar factors for each pixel. Upon selected by the column selection unit 22, the signals accumulated in the CDS circuit 23 are readout thorough the horizontal signal wiring 24 to the circuit at the subsequent stage such as AGC (automatic gain control) and the like, and are processed subsequently.
The wirings shown in FIG. 1 are formed using a plurality of metal wirings. These wirings are the drive wirings such as the transfer signal wiring 11, reset signal wiring 12, and selection signal wiring 13; the signal output wirings such as the pixel output wiring 14, and horizontal signal wiring 24; the power supply wiring 10; and the ground wiring 33. For example, the pixel output wiring 14 to be formed in the vertical direction is formed on the first layer; the drive wirings such as the transfer signal wiring 11, reset signal wiring 12, and selection signal wiring 13 to be formed in the vertical direction, and the ground wiring 33, are formed on the second layer; and the power supply wiring 10 is formed on the third layer.
In addition, in order to connect the power supply wiring 10 and drive wirings with the diffusion region and gate electrode used as the source or drain of the pixel transistor, the connections are provided from the third layer to the second layer, from the second layer to the first layer, and from the first layer to the diffusion region and gate electrode, successively, via through-holes formed in insulating interlayers. In the front-illuminated CMOS image sensor which is configured to focus light through these plural metal wirings onto the photoelectric conversion element, by forming the wirings so as to avoid immediate above the photoelectric conversion element, vignetting caused by the metal wiring is reduced and the focusing efficiency is increased. With the increase in the number of wiring layers, the decrease in the focusing efficiency is generally inevitable from the increase in costs and aspect ratio.
As a further role of the metal wiring, blocking light between pixels can be cited. On reaching the surface of image sensor, light beams are focused onto each photoelectric conversion element through on-chip lens. However, when the incidence angle of the beams is large, there arises the possibility of the light beams to be incident deflected onto the location other than the originally intended photoelectric conversion element. In the case where the beams enter the next photoelectric conversion element, color mixing takes place and the degradation in image quality arises such as the decrease in image resolution, for example. By contrast, by disposing metal wirings between the photoelectric conversion elements, the color mixing to neighboring pixels is suppressed and the degradation in image quality can be prevented. In addition, another structure including dummy wirings is also proposed for the shading between pixels (cf. Japanese Unexamined Patent Application Publication No. 2005-277404).
FIG. 3 is a schematic view illustrating the previously known wiring structure included in the imaging section. Referring to FIG. 3, wirings are formed with a three-layer structure. That is, a pixel output wiring 14 is formed of metal wiring extending in the vertical direction on a first layer. A transfer signal wiring 11, reset signal wiring 12, and selection signal wiring 13 used as drive wirings, and a ground wiring 33 are formed of metal wirings extending in the horizontal direction in parallel to each other on a second layer. A power supply wiring 10 is formed of metal wiring to be in the shape of lattice on a third layer. In order to connect the power supply wiring and drive wirings with diffusion regions and gate electrodes of the pixel transistors, the connections are provided in practice, as mentioned earlier, from the third layer to the second layer, from the second layer to the first layer, and then from the first layer. However, the details thereof are omitted here in the drawing. The power supply wiring 10 on the third layer also serves the role of shading between the pixels.
In addition, another wiring circuit of a CMOS solid-state imaging device is described in Japanese Unexamined Patent Application Publication No. 2003-230055, shading films included in CCD solid-state imaging device are described in Japanese Unexamined Patent Application Publication No. 2005-216886 and Japanese Unexamined Patent Application Publication No. Heisei 11 (1999)-204768, and further shading films included in a CMOS solid-state imaging device are described in Japanese Unexamined Patent Application Publication No. 2004-104203.